This action causes an interrupt, and Windows then calls the ISR with the message content (value) and the address where the message was delivered. In the MSI model, a device delivers a message to its driver by writing to a specific memory address. Although it remains an optional component of the standard that is seldom found in client machines, an increasing number of servers and workstations implement MSI support, which is fully supported by the all recent versions of Windows. In many cases, the hardware has the final decision as to which processor will be interrupted out of the possible set that the Plug and Play manager selected for this interrupt, and there is little device drivers can do.Ī solution to all these problems is a new interrupt mechanism first introduced in the PCI 2.2 standard called message-signaled interrupts (MSI). Finally, line-based interrupts provide poor scalability in multiprocessor environments. (Furthermore, the interrupt controller must typically receive an EOI signal as well.) If either of these does not happen due to a bug, the system can end up in an interrupt state forever, further interrupts could be masked away, or both. Other problems with generating interrupts through an IRQ line is that incorrect management of the IRQ signal can lead to interrupt storms or other kinds of deadlocks on the machine, because the signal is driven “high” or “low” until the ISR acknowledges it.

Additionally, PCI devices are each connected to only one IRQ line anyway, so the media card reader cannot use more than one IRQ in the first place.

However, consuming four IRQ lines for a single device quickly leads to IRQ line exhaustion. For example, in the previous example of the 7-in-1 media card reader, a much better solution is for each device to have its own interrupt and for one driver to manage the different interrupts knowing which device they came from. They are typically undesirable and a side effect of the limited number of physical interrupt lines on a computer. Shared interrupts are often the cause of high interrupt latency and can also cause stability issues. or another attempt to improve latenciesįrom 'Windows Internals' by Mark Russinovich, David A.

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